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    • Deep understanding of Metric driven verification, functional and code coverage.
    • Understanding of directed and constrained random methodologies.
    • Experience in Testbench design with standard verification frameworks like UVM/OVM.
    • Proficient in the languages used for testcase development (C, Verilog, System Verilog … )
    • Knowledge and experience of formal verification methodologies and assertions
    • Understanding of the architecture, elements and functionality of SOCs, including CPUs, DMA, MMU, PLLS, memory and peripheral interfaces.
    • Experience in verification of SOCs with significant analog content is a bonus.
    • Knowledge of product and IC/IP design processes.
    • Understanding of software development process for embedded CPUs and experience in developing and debugging software.
    • Expertise in the use of EDA tools for the developement, simulation and debug of functional tests (RTL simulators, C compilers, debuggers )
    • Experience with debug on designs pre and post-silicon, in simulation and on the bench.
    • Degree in Engineering with 5+ years of experience.
    •  

    Personal Traits:

    • Flexible and adaptable with an ability to verify and debug at many levels and on many different platforms.
    • Rigourous and methodical with good analytical skills
    • Pays attention to details, tenacity in tracing and finding problems
    • Ability to question and identify weaknessess in written specifications
    • Good team player with ability to work across teams and sites.


    Job no. DVE/Sii/04.2019

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